Sony press release:
Sony Develops a Stacked CMOS Image Sensor Technology Using Sony’s Proprietary Global Shutter Function with Back-Illuminated Pixel Structure to Deliver Both High Imaging Performance and Miniaturization
Improves Productivity of Industrial Equipment for Smartification
Tokyo, Japan — Sony Corporation announced today that it has succeed in developing Pregius S, a stacked CMOS image sensor technology that employs Sony’s proprietary global shutter function with back-illuminated pixel structure to deliver both distortion-free, high imaging performance and miniaturization. The new sensor technology is intended for industrial equipment used in fields such as manufacturing, inspection, and logistics that require higher precision and higher processing speeds, in light of the trends in industrial advancement including factory smartification and automation.
Sony will introduce the new technology at Vision China Shanghai 2019 starting on March 20, 2019.
Conventional CMOS image sensors equipped with global shutter function temporarily store charge signals in the memory area located next to the photodiode to resolve image distortion (focal plane distortion) caused by the time shift due to the row-by-row readout. In front-illuminated CMOS image sensors, there is a wiring layer on the silicon substrate forming the photodiode, and with such a structure, the benefit is that it is easy to form a light shield for protecting the charge signal temporarily stored in the memory area from leaked light. For this reason, conventional CMOS image sensors with global shutter function have adopted a front-illuminated pixel structure. However, the wiring on top of the photodiode hinders the incident light, which creates an issue when attempting to miniaturize the pixels.
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In response to this, Sony has developed a proprietary pixel structure that achieves the global shutter function on a back-illuminated structure that has superior sensitivity characteristics, thereby resolving the issue of miniaturization. Normally, when pixels are miniaturized, the sensitivity and saturation characteristics deteriorate, but the new Sony technology enables a reduction in pixel size to 2.74 μm while maintaining performance of those characteristic, thereby achieving about 1.7 times higher resolution than conventional front-illuminated CMOS image sensors.*1 This makes it possible to measure and inspect objects in a wider area and with higher accuracy in manufacturing, inspection, logistics and other applications. Moreover, thanks to the high degree of freedom of the wiring layout of back-illuminated pixel structures, a high speed of about 2.4 times that of conventional*1 can be achieved, thereby contributing to significant productivity improvement, including shorter measurement and inspection process times. In addition, the sensor’s stacked structure makes it possible to mount various signal processing circuits, whereby it is possible to realize smart functions such as signal processing only for the necessary part of the measurement and inspection images in a smaller size compared to conventional sensors.*1 That, in turn, makes it possible to reduce the load of the subsequent processing and reduce the amount of data to be held on to, thereby contributing to the realization of highly efficient, energy-saving systems.
Going forward, Sony will work to develop products equipped with this stacked CMOS image sensor employing its proprietary global shutter function with back-illuminated pixel structure for various industrial applications and intelligent transportation systems, including development of derivatives for signal processing circuits to be mounted. Sony plans to start shipping sample units in the summer of 2019 or later.
1) Proprietary global shutter function with back-illuminated pixel structure delivers both distortion-free high imaging performance and miniaturization
Sony developed a proprietary pixel structure that achieves a global shutter function on a back-illuminated structure that has superior sensitivity characteristics, delivering both high imaging performance and miniaturization. By miniaturizing the pixel size from the conventional*1 3.45 μm to 2.74 μm while maintaining sensitivity and saturation characteristics, Sony has achieved about 1.7 times higher resolution than the conventional front-illuminated 12 megapixels*2 CMOS image sensor,*1 thereby making it possible to perform measurement and inspection in a wider area and at a higher accuracy. Moreover, thanks to the high degree of freedom of the wiring layout of the back-illuminated pixel structure, it is possible to deliver high-speed performance of about 2.4 times that of the conventional technology*1, thereby contributing to significant productivity improvement such as shorter measurement and inspection process times.
2) Miniaturization and high functionality made possible with a stacked structure
The sensor’s stacked structure makes it possible to mount various signal processing circuits, thereby contributing to miniaturization and enhanced functions for CMOS image sensors. Incorporating the data optimization functions (smart ROI, self-trigger, compression processing, compositing, etc.) that extracts only necessary information from the image data, it is possible to reduce the load of the subsequent processing and reduce the amount of data to be held onto while achieving a smaller package compared to conventional sensors,*1 thereby contributing to the realization of highly efficient, energy-saving systems.
Going forward, Sony will leverage the technology of Pregius S to further enhance and expand functions for new industries, including development of derivatives for signal processing circuits to be mounted.